apic.h

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// MIT License
//
// Copyright (c) 2026 Christian Spoo
//
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all
// copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
// SOFTWARE.

 
#ifndef _MINIOS_ARCH_X86_64_APIC_H_
#define _MINIOS_ARCH_X86_64_APIC_H_
 
#include <miniOS/types.h>
 
/* ------------------------------------------------------------------ */
/*  LAPIC MMIO register offsets (byte offsets from lapic_base)         */
/* ------------------------------------------------------------------ */
#define LAPIC_ID          0x020  /* Local APIC ID register             */
#define LAPIC_EOI         0x0B0  /* End-of-Interrupt register          */
#define LAPIC_SVR         0x0F0  /* Spurious Interrupt Vector Register */
#define LAPIC_ICR_LOW     0x300  /* Interrupt Command Register low     */
#define LAPIC_ICR_HIGH    0x310  /* Interrupt Command Register high    */
#define LAPIC_TIMER_LVT   0x320  /* LVT Timer register                 */
#define LAPIC_TIMER_ICR   0x380  /* Timer Initial Count Register       */
#define LAPIC_TIMER_CCR   0x390  /* Timer Current Count Register       */
#define LAPIC_TIMER_DCR   0x3E0  /* Timer Divide Configuration Register*/
 
/* ------------------------------------------------------------------ */
/*  SVR flags                                                          */
/* ------------------------------------------------------------------ */
#define LAPIC_SVR_ENABLE       (1 << 8)  /* Software enable bit        */
#define LAPIC_SPURIOUS_VECTOR  0xFF      /* Spurious interrupt vector  */
 
/* ------------------------------------------------------------------ */
/*  IA32_APIC_BASE MSR                                                 */
/* ------------------------------------------------------------------ */
#define IA32_APIC_BASE_MSR    0x1B
#define IA32_APIC_BASE_ENABLE (1 << 11)  /* Global enable bit          */
 
/* ------------------------------------------------------------------ */
/*  LAPIC base pointer (set by lapic_init)                             */
/* ------------------------------------------------------------------ */
extern volatile uint32_t *lapic_base;
 
/* ------------------------------------------------------------------ */
/*  Public API                                                         */
/* ------------------------------------------------------------------ */

void lapic_init(void);

static inline void lapic_write(uint32_t reg, uint32_t val) {
    lapic_base[reg / 4] = val;
}

static inline uint32_t lapic_read(uint32_t reg) {
    return lapic_base[reg / 4];
}

static inline void lapic_eoi(void) {
    lapic_write(LAPIC_EOI, 0);
}

void lapic_eoi_asm(void);

void lapic_send_ipi(uint8_t target_lapic_id, uint8_t vector);
 
/* ------------------------------------------------------------------ */
/*  I/O APIC MMIO base (physical).                                    */
/*  Identity-mapped via page_table_l2_mmio L2[502] (2MB huge page).  */
/* ------------------------------------------------------------------ */
#define IOAPIC_BASE         0xFEC00000UL
/* I/O APIC indirect registers (byte offsets from IOAPIC_BASE) */
#define IOAPIC_REGSEL       0x00   /* register select */
#define IOAPIC_IOWIN        0x10   /* data window */
/* I/O APIC indirect register indices */
#define IOAPIC_ID           0x00
#define IOAPIC_VER          0x01
#define IOAPIC_REDTBL_LO(n) (0x10 + (n)*2)     /* low 32 bits of redirection entry n */
#define IOAPIC_REDTBL_HI(n) (0x10 + (n)*2 + 1) /* high 32 bits of redirection entry n */
/* Redirection entry bits */
#define IOAPIC_RTE_MASKED   (1 << 16)           /* set to mask (disable) this IRQ line */
#define IOAPIC_RTE_LEVEL    (1 << 15)           /* 0=edge, 1=level trigger */
#define IOAPIC_RTE_LOPOL    (1 << 13)           /* 0=active-high, 1=active-low polarity */
/* First IDT vector for external IRQs (vectors 0-31 are CPU exceptions) */
#define IRQ_VECTOR_BASE     32

void ioapic_init(void);

void ioapic_mask_irq(uint8_t irq);

void ioapic_unmask_irq(uint8_t irq);
 
/* ------------------------------------------------------------------ */
/*  LAPIC timer                                                        */
/* ------------------------------------------------------------------ */
#define LAPIC_TIMER_PERIODIC    (1 << 17)   /* LVT timer mode: periodic */
#define LAPIC_TIMER_ONESHOT     (0 << 17)   /* LVT timer mode: one-shot */
#define LAPIC_TIMER_MASKED      (1 << 16)   /* LVT: mask the timer      */
#define LAPIC_TIMER_VECTOR      48          /* IDT vector for LAPIC timer */
#define SCHEDULER_KICK_VECTOR   50          /* IDT vector: scheduler-kick IPI from remote CPU */
#define PANIC_HALT_VECTOR       52          /* IDT vector: panic-halt IPI broadcast */
/* IDT vectors 53..53+MAX_CPUS-1: one dedicated TLB-shootdown IPI vector per
 * possible INITIATOR CPU (hardcoded to 8 — must match MAX_CPUS's default in
 * smp.h; there is no build-system plumbing to pass MAX_CPUS into the NASM
 * assembler). Giving each initiator its own vector (and barrier slot, see
 * ipi.h) means concurrent shootdowns started by different CPUs never share
 * mutable state — see ipi.c for why a single shared vector/barrier isn't
 * safe under SMP. */
#define TLB_SHOOTDOWN_VECTOR_BASE 53
#define LAPIC_TIMER_DIVBY_16    0x3         /* DCR divide-by-16         */

void lapic_timer_idt_install(void);

void lapic_timer_init(void);
extern volatile uint64_t lapic_tick_count;
 
/* BSP-calibrated LAPIC timer ICR value (written by lapic_timer_init).
   APs read this to start their timers without running PIT calibration again. */
extern uint32_t lapic_bsp_timer_icr;

void lapic_timer_init_ap(void);

 
#endif /* _MINIOS_ARCH_X86_64_APIC_H_ */