34#ifndef _MINIOS_ARCH_X86_64_SMP_H_
35#define _MINIOS_ARCH_X86_64_SMP_H_
95 __asm__
volatile(
"mov %%gs:0, %0" :
"=r"(p) ::
"memory");
volatile uint32_t smp_aps_ready
Definition smp_boot.c:44
void cpu_enable_sse(void)
Enable SSE/SSE2 on the calling CPU.
Definition main.c:134
void acpi_find_madt(uint64_t mb_info_phys)
Parse ACPI MADT and populate smp_lapic_ids[]/smp_cpu_count.
Definition acpi.c:204
void ap_barrier_checkin(void)
Signal that this AP has completed its CPU init.
Definition smp_boot.c:48
void per_cpu_init(uint32_t cpu_id)
Initialise per-CPU GDT, TSS, IDT, and GS base for one CPU.
Definition per_cpu.c:61
static cpu_t * cpu_local(void)
Definition smp.h:93
cpu_t g_cpus[MAX_CPUS]
Definition per_cpu.c:49
uint32_t smp_cpu_count
Definition acpi.c:32
#define MAX_CPUS
Definition smp.h:42
uint8_t smp_lapic_ids[MAX_CPUS]
Definition acpi.c:33
void smp_boot_aps(void)
Send INIT-SIPI-SIPI sequence to all non-BSP CPUs.
Definition smp_boot.c:166
void per_cpu_update_rsp0(uint64_t rsp0)
Update this CPU's TSS RSP0 and cpu_t.kstack_top.
Definition per_cpu.c:55
void smp_wait_for_aps(void)
Block until all APs have checked in at the rendezvous barrier.
Definition smp_boot.c:55
void lapic_timer_init_ap(void)
Start LAPIC timer on the calling AP using the BSP-calibrated ICR.
Definition lapic.c:257
uint64_t kstack_top
Definition smp.h:81
uint8_t * kstack_base
Definition smp.h:72
uint32_t lapic_id
Definition smp.h:70
struct thread * current_thread
Definition smp.h:80
uint64_t user_rsp_scratch
Definition smp.h:82
struct thread * run_queue_tail
Definition smp.h:78
uint32_t queue_depth
Definition smp.h:79
struct thread * run_queue_head
Definition smp.h:77
struct thread * idle_thread
Definition smp.h:71
uint32_t cpu_id
Definition smp.h:69
struct cpu_t * self
Definition smp.h:68
unsigned int uint32_t
Definition types.h:34
unsigned long int uint64_t
Definition types.h:37
unsigned char uint8_t
Definition types.h:28