ata.h

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// MIT License
//
// Copyright (c) 2026 Christian Spoo
//
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all
// copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
// SOFTWARE.
 
#ifndef _MINIOS_DRIVERS_ATA_H_
#define _MINIOS_DRIVERS_ATA_H_
 
#include <miniOS/types.h> 
 
 
/* ATA I/O base ports */
#define ATA_PRIMARY_BASE    0x1F0
#define ATA_PRIMARY_CTRL    0x3F6
#define ATA_SECONDARY_BASE  0x170
#define ATA_SECONDARY_CTRL  0x376
 
/* IRQ lines */
#define ATA_PRIMARY_IRQ     14
#define ATA_SECONDARY_IRQ   15
 
/* Drive select patterns */
#define ATA_MASTER          0xA0
#define ATA_SLAVE           0xB0
 
/* ATA register offsets from base port */
#define ATA_REG_DATA        0x00
#define ATA_REG_ERROR       0x01    /* read */
#define ATA_REG_FEATURES    0x01    /* write */
#define ATA_REG_SECCOUNT0   0x02
#define ATA_REG_LBA0        0x03
#define ATA_REG_LBA1        0x04
#define ATA_REG_LBA2        0x05
#define ATA_REG_HDDEVSEL    0x06
#define ATA_REG_STATUS      0x07    /* read */
#define ATA_REG_COMMAND     0x07    /* write */
 
/* ATA status register bits */
#define ATA_SR_BSY          0x80
#define ATA_SR_DRDY         0x40
#define ATA_SR_DRQ          0x08
#define ATA_SR_ERR          0x01
 
/* Bus Mastering DMA register offsets from BMR base port */
#define BMR_CMD             0x00    /* bit 0 = start/stop, bit 3 = dir (0=read) */
#define BMR_STATUS          0x02    /* bit 0 = active, bit 1 = error, bit 2 = IRQ */
#define BMR_PRDT            0x04    /* 32-bit physical address of PRD table */
 
/* ATA and DMA size constants */
#define SECTOR_SIZE         512    /* bytes per ATA sector */
#define MAX_SECTORS_PER_RW  8     /* 8 x 512 B = 4 KiB bounce buffer */
 
/* ATA commands */
#define ATA_CMD_READ_DMA_EXT  0x25  /* READ DMA EXT (48-bit LBA) */
#define ATA_CMD_WRITE_DMA_EXT  0x35  /* WRITE DMA EXT (48-bit LBA) */
#define ATA_CMD_CACHE_FLUSH_EXT 0xEA /* CACHE FLUSH EXT — flushes write-back cache */
 
/* PRD table entry flag */
#define PRD_LAST_ENTRY      0x8000  /* bit 15 = last entry in PRD table */
 
/* BMR_STATUS bit masks */
#define BMR_ACTIVE_BIT      0x01   /* DMA transfer in progress */
#define BMR_ERROR_BIT       0x02   /* DMA error occurred */
#define BMR_IRQ_BIT         0x04   /* IRQ fired (DMA complete) */
#define BMR_START_BIT       0x01   /* BMR_CMD bit 0: start DMA */
 
/* Physical Region Descriptor entry — 8 bytes, 4-byte aligned */
typedef struct {
    uint32_t phys_addr;     /* physical base of transfer buffer */
    uint16_t byte_count;    /* 0 means 65536 bytes */
    uint16_t flags;         /* bit 15 = 1 -> last entry in table */
} __attribute__((packed)) prd_entry_t;

int ata_init(void);

int ata_read_sectors(uint64_t lba, uint16_t count, void *buf);

int ata_write_sectors(uint64_t lba, uint16_t count, const void *buf);

int ata_flush(void);
 
#endif /* _MINIOS_DRIVERS_ATA_H_ */