miniOS
x86_64 hobby kernel with SMP, VFS, and POSIX process model
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ipi.h
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1// MIT License
2//
3// Copyright (c) 2026 Christian Spoo
4//
5// Permission is hereby granted, free of charge, to any person obtaining a copy
6// of this software and associated documentation files (the "Software"), to deal
7// in the Software without restriction, including without limitation the rights
8// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
9// copies of the Software, and to permit persons to whom the Software is
10// furnished to do so, subject to the following conditions:
11//
12// The above copyright notice and this permission notice shall be included in all
13// copies or substantial portions of the Software.
14//
15// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21// SOFTWARE.
22
36
37#ifndef _MINIOS_IPI_IPI_H_
38#define _MINIOS_IPI_IPI_H_
39
40#include <miniOS/types.h>
43
52typedef struct {
53 volatile uint32_t ack_count; /* decremented by each handler */
54 uint64_t virt; /* virtual address for TLB shootdown */
56
57/* One TLB-shootdown barrier PER INITIATOR CPU, indexed by the initiating
58 * CPU's cpu_id. A shootdown started by CPU N always uses g_tlb_barriers[N]
59 * and is announced on the dedicated vector TLB_SHOOTDOWN_VECTOR_BASE + N
60 * (see tlb_shootdown_isr_n() in ipi.c). This means two CPUs initiating a
61 * shootdown at the same time never touch the same barrier struct — no lock
62 * needed, and no risk of one initiator's ack_count/virt being clobbered by
63 * another's concurrent call — with a single shared barrier, two concurrent
64 * initiators can flush the wrong address on remote CPUs and drive ack_count
65 * below zero (wraps, since it's unsigned), making ipi_barrier_wait() spin
66 * forever. */
68
73static inline void ipi_barrier_ack(ipi_barrier_t *b) {
74 __asm__ volatile("lock subl $1, %0" : "+m"(b->ack_count) : : "memory");
75}
76
81static inline void ipi_barrier_wait(ipi_barrier_t *b) {
82 while (b->ack_count > 0)
83 __asm__ volatile("pause" : : : "memory");
84}
85
106void ipi_tlb_shootdown(uint64_t virt);
107
118void tlb_shootdown_isr(uint32_t src_cpu);
119
128void ipi_panic_halt(void);
129
137void panic_halt_isr(void *frame);
138
140
141#endif /* _MINIOS_IPI_IPI_H_ */
void panic_halt_isr(void *frame)
ISR for PANIC_HALT_VECTOR (52) on APs.
Definition ipi.c:116
ipi_barrier_t g_tlb_barriers[MAX_CPUS]
Definition ipi.c:30
void ipi_panic_halt(void)
Broadcast halt IPI to all APs on kernel panic.
Definition ipi.c:77
void tlb_shootdown_isr(uint32_t src_cpu)
ISR for TLB_SHOOTDOWN_VECTOR_BASE + N on remote CPUs (one per possible initiator CPU N — see tlb_shoo...
Definition ipi.c:63
static void ipi_barrier_ack(ipi_barrier_t *b)
Atomically decrement the barrier's ack_count.
Definition ipi.h:73
void ipi_tlb_shootdown(uint64_t virt)
Broadcast TLB-shootdown IPI and wait for all CPUs to flush.
Definition ipi.c:32
static void ipi_barrier_wait(ipi_barrier_t *b)
Spin until barrier->ack_count reaches 0.
Definition ipi.h:81
#define MAX_CPUS
Definition smp.h:42
Definition ipi.h:52
uint64_t virt
Definition ipi.h:54
volatile uint32_t ack_count
Definition ipi.h:53
unsigned int uint32_t
Definition types.h:34
unsigned long int uint64_t
Definition types.h:37