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x86_64 hobby kernel with SMP, VFS, and POSIX process model
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ipi.h
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// MIT License
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//
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// Copyright (c) 2026 Christian Spoo
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy
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// of this software and associated documentation files (the "Software"), to deal
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// in the Software without restriction, including without limitation the rights
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// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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// copies of the Software, and to permit persons to whom the Software is
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// furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all
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// copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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// SOFTWARE.
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#ifndef _MINIOS_IPI_IPI_H_
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#define _MINIOS_IPI_IPI_H_
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#include <
miniOS/types.h
>
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#include <
miniOS/arch/x86_64/spinlock.h
>
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#include <
miniOS/arch/x86_64/smp.h
>
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typedef
struct
{
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volatile
uint32_t
ack_count
;
/* decremented by each handler */
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uint64_t
virt
;
/* virtual address for TLB shootdown */
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}
ipi_barrier_t
;
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/* One TLB-shootdown barrier PER INITIATOR CPU, indexed by the initiating
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* CPU's cpu_id. A shootdown started by CPU N always uses g_tlb_barriers[N]
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* and is announced on the dedicated vector TLB_SHOOTDOWN_VECTOR_BASE + N
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* (see tlb_shootdown_isr_n() in ipi.c). This means two CPUs initiating a
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* shootdown at the same time never touch the same barrier struct — no lock
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* needed, and no risk of one initiator's ack_count/virt being clobbered by
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* another's concurrent call — with a single shared barrier, two concurrent
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* initiators can flush the wrong address on remote CPUs and drive ack_count
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* below zero (wraps, since it's unsigned), making ipi_barrier_wait() spin
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* forever. */
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extern
ipi_barrier_t
g_tlb_barriers
[
MAX_CPUS
];
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static
inline
void
ipi_barrier_ack
(
ipi_barrier_t
*b) {
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__asm__
volatile
(
"lock subl $1, %0"
:
"+m"
(b->
ack_count
) : :
"memory"
);
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}
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static
inline
void
ipi_barrier_wait
(
ipi_barrier_t
*b) {
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while
(b->
ack_count
> 0)
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__asm__
volatile
(
"pause"
: : :
"memory"
);
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}
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void
ipi_tlb_shootdown
(
uint64_t
virt);
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void
tlb_shootdown_isr
(
uint32_t
src_cpu);
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void
ipi_panic_halt
(
void
);
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void
panic_halt_isr
(
void
*frame);
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#endif
/* _MINIOS_IPI_IPI_H_ */
panic_halt_isr
void panic_halt_isr(void *frame)
ISR for PANIC_HALT_VECTOR (52) on APs.
Definition
ipi.c:116
g_tlb_barriers
ipi_barrier_t g_tlb_barriers[MAX_CPUS]
Definition
ipi.c:30
ipi_panic_halt
void ipi_panic_halt(void)
Broadcast halt IPI to all APs on kernel panic.
Definition
ipi.c:77
tlb_shootdown_isr
void tlb_shootdown_isr(uint32_t src_cpu)
ISR for TLB_SHOOTDOWN_VECTOR_BASE + N on remote CPUs (one per possible initiator CPU N — see tlb_shoo...
Definition
ipi.c:63
ipi_barrier_ack
static void ipi_barrier_ack(ipi_barrier_t *b)
Atomically decrement the barrier's ack_count.
Definition
ipi.h:73
ipi_tlb_shootdown
void ipi_tlb_shootdown(uint64_t virt)
Broadcast TLB-shootdown IPI and wait for all CPUs to flush.
Definition
ipi.c:32
ipi_barrier_wait
static void ipi_barrier_wait(ipi_barrier_t *b)
Spin until barrier->ack_count reaches 0.
Definition
ipi.h:81
MAX_CPUS
#define MAX_CPUS
Definition
smp.h:42
smp.h
spinlock.h
ipi_barrier_t
Definition
ipi.h:52
ipi_barrier_t::virt
uint64_t virt
Definition
ipi.h:54
ipi_barrier_t::ack_count
volatile uint32_t ack_count
Definition
ipi.h:53
types.h
uint32_t
unsigned int uint32_t
Definition
types.h:34
uint64_t
unsigned long int uint64_t
Definition
types.h:37
include
miniOS
ipi
ipi.h
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